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| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | 2021-02-04 13:16:24 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:23:22 +0000 |
| commit | 3c6ad8d1843d63c37c8f413263fd140fa78f866a (patch) | |
| tree | f35d730c51677399d1e057924c7a92e742710501 /src/arch/x86/timestamp.c | |
| parent | fbad99f347957871269d197b80df18e2912c622f (diff) | |
mb/google/volteer: Enable external bypass, clkgate & phygate
This change sets the soc config options for external_bypass,
external_clk_gate and external_phy_gate.
BUG=b:177821896
TEST=Build coreboot for volteer
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: I9e5218cda79d7453bf830639ccea4e5be019b070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50290
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/timestamp.c')
0 files changed, 0 insertions, 0 deletions