diff options
author | Aaron Durbin <adurbin@chromium.org> | 2015-09-04 12:06:05 -0500 |
---|---|---|
committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:35:12 +0000 |
commit | 14714e1303a420f9e0bf0bb5bba2efaae2c52efb (patch) | |
tree | c26b86718fb5de9ef1e2194071f640f51e0a1149 /src/arch/x86/romstage.ld | |
parent | b2a62622ba030162784c31865a4fcba0c03408c7 (diff) |
x86: link romstage like the other architectures
All the other architectures are using the memlayout
for linking romstage. Use that same method on x86
as well for consistency.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built a myriad of boards. Analyzed readelf output.
Change-Id: I016666c4b01410df112e588c2949e3fc64540c2e
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11510
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86/romstage.ld')
-rw-r--r-- | src/arch/x86/romstage.ld | 46 |
1 files changed, 10 insertions, 36 deletions
diff --git a/src/arch/x86/romstage.ld b/src/arch/x86/romstage.ld index cc0142eb80..d6d1b9c684 100644 --- a/src/arch/x86/romstage.ld +++ b/src/arch/x86/romstage.ld @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Advanced Micro Devices, Inc. * Copyright (C) 2008-2010 coresystems GmbH + * Copyright 2015 Google Inc * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,52 +19,25 @@ * Foundation, Inc. */ -TARGET(binary) +#include <memlayout.h> +#include <arch/header.ld> + SECTIONS { - . = ROMSTAGE_BASE; - - .rom . : { - _rom = .; - *(.rom.text); - *(.rom.data); - *(.text); - *(.text.*); - . = ALIGN(4); - _cbmem_init_hooks = .; - KEEP(*(.rodata.cbmem_init_hooks)); - _ecbmem_init_hooks = .; - *(.rodata); - *(.rodata.*); - . = ALIGN(16); - _erom = .; - } - - /DISCARD/ : { - *(.comment) - *(.note) - *(.comment.*) - *(.note.*) - *(.eh_frame); - } + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) . = CONFIG_DCACHE_RAM_BASE; .car.data . (NOLOAD) : { _car_data_start = .; #if IS_ENABLED(CONFIG_HAS_PRECBMEM_TIMESTAMP_REGION) - _timestamp = .; - . = . + 0x100; - _etimestamp = .; + TIMESTAMP(., 0x100) #endif *(.car.global_data); + . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _car_data_end = .; - /* The preram cbmem console area comes last to take advantage - * of a zero-sized array to hold the memconsole contents. - * However, collisions within the cache-as-ram region cannot be - * statically checked because the cache-as-ram region usage is - * cpu/chipset dependent. */ - _preram_cbmem_console = .; - _epreram_cbmem_console = . + (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00); + + PRERAM_CBMEM_CONSOLE(., (CONFIG_LATE_CBMEM_INIT ? 0 : 0xc00)) } /* Global variables are not allowed in romstage |