New mechanism to define SRAM/memory map with automatic bounds checking

This patch creates a new mechanism to define the static memory layout
(primarily in SRAM) for a given board, superseding the brittle mass of
Kconfigs that we were using before. The core part is a memlayout.ld file
in the mainboard directory (although boards are expected to just include
the SoC default in most cases), which is the primary linker script for
all stages (though not rmodules for now). It uses preprocessor macros
from <memlayout.h> to form a different valid linker script for all
stages while looking like a declarative, boilerplate-free map of memory
addresses to the programmer. Linker asserts will automatically guarantee
that the defined regions cannot overlap. Stages are defined with a
maximum size that will be enforced by the linker. The file serves to
both define and document the memory layout, so that the documentation
cannot go missing or out of date.

The mechanism is implemented for all boards in the ARM, ARM64 and MIPS
architectures, and should be extended onto all systems using SRAM in the
future. The CAR/XIP environment on x86 has very different requirements
and the layout is generally not as static, so it will stay like it is
and be unaffected by this patch (save for aligning some symbol names for
consistency and sharing the new common ramstage linker script include).

BUG=None
TEST=Booted normally and in recovery mode, checked suspend/resume and
the CBMEM console on Falco, Blaze (both normal and vboot2), Pinky and
Pit. Compiled Ryu, Storm and Urara, manually compared the disassemblies
with ToT and looked for red flags.

Change-Id: Ifd2276417f2036cbe9c056f17e42f051bcd20e81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f1e2028e7ebceeb2d71ff366150a37564595e614
Original-Change-Id: I005506add4e8fcdb74db6d5e6cb2d4cb1bd3cda5
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/213370
Reviewed-on: http://review.coreboot.org/9283
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-by: Aaron Durbin <adurbin@google.com>

1 files changed, 7 insertions, 110 deletions

diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld
index f765cbe6f9..5fcbbb632a 100644
--- a/src/arch/x86/ramstage.ld
+++ b/src/arch/x86/ramstage.ld
@@ -8,121 +8,18 @@
  *				: stack
  *				: heap
  */
-/*
- * Bootstrap code for the STPC Consumer
- * Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
- */
-
-/*
- *	Written by Johan Rydberg, based on work by Daniel Kahlin.
- *      Rewritten by Eric Biederman
- *  2005.12 yhlu add ramstage cross the vga font buffer handling
- */
-
 ENTRY(_start)
 
+PHDRS
+{
+	to_load PT_LOAD;
+}
+
 SECTIONS
 {
 	. = CONFIG_RAMBASE;
-	/* First we place the code and read only data (typically const declared).
-	 * This could theoretically be placed in rom.
-	 */
-	.text : {
-		_text = .;
-		*(.textfirst);
-		*(.text);
-		*(.text.*);
-		. = ALIGN(16);
-		_etext = .;
-	}
-
-	.ctors : {
-		. = ALIGN(0x100);
-		__CTOR_LIST__ = .;
-		KEEP(*(.ctors));
-		LONG(0);
-		__CTOR_END__ = .;
-	}
-
-	.rodata : {
-		_rodata = .;
-		. = ALIGN(4);
-
-		/* If any changes are made to the driver start/symbols or the
-		 * section names the equivalent changes need to made to
-		 * rmodule.ld. */
-		pci_drivers = . ;
-		KEEP(*(.rodata.pci_driver));
-		epci_drivers = . ;
-		cpu_drivers = . ;
-		KEEP(*(.rodata.cpu_driver));
-		ecpu_drivers = . ;
-		_bs_init_begin = .;
-		KEEP(*(.bs_init));
-		LONG(0);
-		_bs_init_end = .;
-
-		*(.rodata)
-		*(.rodata.*)
-		/* kevinh/Ispiri - Added an align, because the objcopy tool
-		 * incorrectly converts sections that are not long word aligned.
-		 */
-		 . = ALIGN(4);
-
-		_erodata = .;
-	}
-	/* After the code we place initialized data (typically initialized
-	 * global variables). This gets copied into ram by startup code.
-	 * __data_start and __data_end shows where in ram this should be placed,
-	 * whereas __data_loadstart and __data_loadend shows where in rom to
-	 * copy from.
-	 */
-	.data : {
-		_data = .;
-		*(.data)
-		*(.data.*)
-		_edata = .;
-	}
-
-	/* bss does not contain data, it is just a space that should be zero
-	 * initialized on startup. (typically uninitialized global variables)
-	 * crt0.S fills between _bss and _ebss with zeroes.
-	 */
-	_bss = .;
-	.bss . : {
-		*(.bss)
-		*(.bss.*)
-		*(.sbss)
-		*(.sbss.*)
-		*(COMMON)
-	}
-	_ebss = .;
-
-        _heap = .;
-        .heap . : {
-                /* Reserve CONFIG_HEAP_SIZE bytes for the heap */
-                . = CONFIG_HEAP_SIZE ;
-                . = ALIGN(4);
-        }
-        _eheap = .;
-
-	/* The ram segment. This includes all memory used by the memory
-	 * resident copy of coreboot, except the tables that are produced on
-	 * the fly, but including stack and heap.
-	 */
-	_ram_seg = _text;
-	_eram_seg = _eheap;
-
-	/* CONFIG_RAMTOP is the upper address of cached memory (among other
-	 * things). We must not exceed beyond that address, there be dragons.
-	 */
-	_bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 
-	/* Discard the sections we don't need/want */
+	INCLUDE "lib/ramstage.ramstage.ld"
 
-	/DISCARD/ : {
-		*(.comment)
-		*(.note)
-		*(.note.*)
-	}
+	_ = ASSERT( ( _eprogram < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP");
 }