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| author | Subrata Banik <subrata.banik@intel.com> | 2019-03-05 16:45:14 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-07 17:21:23 +0000 |
| commit | 4f42eead361b8d6b2f96031bcaf4627f2a5ea8a6 (patch) | |
| tree | 196fe33ef1bc30614a76d6a4a38d81cb57713d84 /src/arch/x86/postcar.c | |
| parent | 34508cd9ac51021721f3e9abfe2a69c8a9835a4b (diff) | |
arch/x86/postcar: Add separate timestamp for postcar stage
This patch adds dedicated timestamp value for postcar stage.
TEST=Able to see "start of postcar" and "end of postcar" timestamp
while executing cbmem -t after booting to chrome console.
> cbmem -t
951:returning from FspMemoryInit 20,485,324 (20,103,067)
4:end of romstage 20,559,235 (73,910)
100:start of postcar 20,560,266 (1,031)
101:end of postcar 20,570,038 (9,772)
Change-Id: I084f66949667ad598f811d4233b4e639bc4c113e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86/postcar.c')
| -rw-r--r-- | src/arch/x86/postcar.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index ea05824e6f..b4efc949b4 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -19,6 +19,7 @@ #include <cpu/x86/mtrr.h> #include <main_decl.h> #include <program_loading.h> +#include <timestamp.h> /* * Systems without a native coreboot cache-as-ram teardown may implement @@ -35,6 +36,8 @@ void main(void) /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); + timestamp_add_now(TS_START_POSTCAR); + display_mtrrs(); /* Load and run ramstage. */ |