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authorNico Huber <nico.h@gmx.de>2018-11-13 19:28:07 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-11-23 08:34:16 +0000
commitd67edcae6e9d438f2e60f6b67d97a7d3f09cb18b (patch)
tree38d7fe7b769f4193ea3b4494dc7944b9718c678c /src/arch/x86/postcar.c
parent3032d7677883eb726d14fcd85efae7a7c068259a (diff)
soc/intel/common: Bring DISPLAY_MTRRS into the light
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the "Debug" menu. It turned out, though, that the code looks rather generic. No need to hide it in soc/intel/. To not bloat src/Kconfig up any further, start a new `Kconfig.debug` hierarchy just for debug options. If somebody wants to review the code if it's 100% generic, we could even get rid of HAVE_DISPLAY_MTRRS. Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/29684 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/postcar.c')
-rw-r--r--src/arch/x86/postcar.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c
index 295276bf8d..ea05824e6f 100644
--- a/src/arch/x86/postcar.c
+++ b/src/arch/x86/postcar.c
@@ -16,9 +16,9 @@
#include <arch/cpu.h>
#include <cbmem.h>
#include <console/console.h>
+#include <cpu/x86/mtrr.h>
#include <main_decl.h>
#include <program_loading.h>
-#include <soc/intel/common/util.h>
/*
* Systems without a native coreboot cache-as-ram teardown may implement
@@ -35,9 +35,7 @@ void main(void)
/* Recover cbmem so infrastruture using it is functional. */
cbmem_initialize();
- /* Display the MTRRs */
- if (IS_ENABLED(CONFIG_DISPLAY_MTRRS))
- soc_display_mtrrs();
+ display_mtrrs();
/* Load and run ramstage. */
run_ramstage();