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authorMichael Niewöhner <foss@mniewoehner.de>2020-11-12 23:50:37 +0100
committerMichael Niewöhner <foss@mniewoehner.de>2022-01-09 01:47:22 +0000
commit02275be61e442e022101b322279940fb0e74f7a8 (patch)
treea921d334544a5603e44debb12a3cb5d4ab980d37 /src/arch/x86/memlayout.ld
parent63660592dc50e9a94c60411fb58b6436755eea01 (diff)
soc/intel/{icl,tgl,jsl,ehl}: enable ACPI CPPC entries
Enable CPPC entries generation, needed for Intel SpeedShift. This can be tested by checking sysfs in Linux: $ grep . /sys/devices/system/cpu/cpu?/acpi_cppc/*perf The output should look like this, while the values may differ: /sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_nonlinear_perf:5 /sys/devices/system/cpu/cpu0/acpi_cppc/lowest_perf:1 /sys/devices/system/cpu/cpu0/acpi_cppc/nominal_perf:24 /sys/devices/system/cpu/cpu1/acpi_cppc/highest_perf:28 /sys/devices/system/cpu/cpu1/acpi_cppc/lowest_nonlinear_perf:5 ... Change-Id: I910b4e17d4044f1bf1ecfa0643ac62fc7a8cb51b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lance Zhao Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sheng Lean Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/arch/x86/memlayout.ld')
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