diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-09-05 13:31:14 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-09-09 19:35:42 +0000 |
| commit | 956c4f2d4cfa2b43085b493e0c5fed2f61cf5363 (patch) | |
| tree | 21155deec46c78623c1179f5b10defcd14f49e4a /src/arch/x86/memlayout.ld | |
| parent | dde7629e9cccf7b3a9b2e468ac8439f91d13cf97 (diff) | |
x86: link romstage and ramstage with 1 file
To reduce file clutter merge romstage.ld and ramstage.ld
into a single memlayout.ld. The naming is consistent with
other architectures and chipsets for their linker script
names. The cache-as-ram linking rules are put into a separate
file such that other rules can be applied for future verstage
support.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi and dmp/vortex86ex.
Change-Id: I1e8982a6a28027566ddd42a71b7e24e2397e68d2
Signed-off-by: Aaron Durbin <adubin@chromium.org>
Reviewed-on: http://review.coreboot.org/11521
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/arch/x86/memlayout.ld')
| -rw-r--r-- | src/arch/x86/memlayout.ld | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld new file mode 100644 index 0000000000..43c522918f --- /dev/null +++ b/src/arch/x86/memlayout.ld @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + /* + * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively + * like other architectures/chipsets it's not possible because of + * the linking games played during romstage creation by trying + * to find the final landing place in CBFS for XIP. Therefore, + * conditionalize with macros. + */ +#if ENV_RAMSTAGE + RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) + +#elif ENV_ROMSTAGE + /* The 1M size is not allocated. It's just for basic size checking. */ + ROMSTAGE(ROMSTAGE_BASE, 1M) + + /* Pull in the cache-as-ram rules. */ + #include "car.ld" +#endif +} |