diff options
author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-06-12 17:30:33 -0700 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-06-17 11:56:01 +0200 |
commit | 2da9524aaf90b6b2f4d7fab81bfc82c9829e3d32 (patch) | |
tree | 54b59f36a0cefd98d8d3286e6bd5bbf7ab3c8609 /src/arch/x86/lib/cpu_common.c | |
parent | 63a3e1ec7f49222c670d08424cbc7fc7f46ee7b0 (diff) |
x86 cpu: Allow some cpuid functions during romstage
Allow calls to cpu_phys_address_size and its support functions during
romstage. This enables the proper display of MTRRs during romstage
without duplicating this code.
BRANCH=none
BUG=None
TEST=Build and run on cyan
Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0
Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/277392
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10561
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86/lib/cpu_common.c')
-rw-r--r-- | src/arch/x86/lib/cpu_common.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/arch/x86/lib/cpu_common.c b/src/arch/x86/lib/cpu_common.c new file mode 100644 index 0000000000..6c5561df98 --- /dev/null +++ b/src/arch/x86/lib/cpu_common.c @@ -0,0 +1,56 @@ +#include <console/console.h> +#include <cpu/cpu.h> +#include <arch/io.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> +#include <device/path.h> +#include <device/device.h> +#include <smp/spinlock.h> + +/* Standard macro to see if a specific flag is changeable */ +static inline int flag_is_changeable_p(uint32_t flag) +{ + uint32_t f1, f2; + + asm( + "pushfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "movl %0,%1\n\t" + "xorl %2,%0\n\t" + "pushl %0\n\t" + "popfl\n\t" + "pushfl\n\t" + "popl %0\n\t" + "popfl\n\t" + : "=&r" (f1), "=&r" (f2) + : "ir" (flag)); + return ((f1^f2) & flag) != 0; +} + +/* Probe for the CPUID instruction */ +int cpu_have_cpuid(void) +{ + return flag_is_changeable_p(X86_EFLAGS_ID); +} + +int cpu_cpuid_extended_level(void) +{ + return cpuid_eax(0x80000000); +} + +int cpu_phys_address_size(void) +{ + if (!(cpu_have_cpuid())) + return 32; + + if (cpu_cpuid_extended_level() >= 0x80000008) + return cpuid_eax(0x80000008) & 0xff; + + if (cpuid_edx(1) & (CPUID_FEATURE_PAE | CPUID_FEATURE_PSE36)) + return 36; + return 32; +} |