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authorPatrick Georgi <patrick.georgi@secunet.com>2012-11-20 11:53:47 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2012-11-27 23:51:52 +0100
commite135ac5a7ea69b6edcb89345019212f5de412b1e (patch)
tree408611a9f2846867f9731af53b1f08dd32eb6851 /src/arch/x86/include
parentbdc1816b2379bdf569ac6746172bba41e1307917 (diff)
Remove AMD special case for LAPIC based udelay()
- Optionally override FSB clock detection in generic LAPIC code with constant value. - Override on AMD Model fxx, 10xxx, agesa CPUs with 200MHz - compile LAPIC code for romstage, too - Remove #include ".../apic_timer.c" in AMD based mainboards - Remove custom udelay implementation from intel northbridges' romstages Future work: - remove the compile time special case (requires some cpuid based switching) - drop northbridge udelay implementations (i945, i5000) if not required anymore (eg. can SMM use the LAPIC timer?) Change-Id: I25bacaa2163f5e96ab7f3eaf1994ab6899eff054 Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Reviewed-on: http://review.coreboot.org/1618 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r--src/arch/x86/include/arch/cpu.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index aa0412fc49..abe3f7fba7 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -138,6 +138,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
+#if !defined(__ROMCC__)
#if !defined(__PRE_RAM__)
#include <device/device.h>
@@ -157,6 +158,10 @@ struct cpu_driver {
struct device;
struct cpu_driver *find_cpu_driver(struct device *cpu);
+#else
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#endif
struct cpu_info {
device_t cpu;