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authorElyes HAOUAS <ehaouas@noos.fr>2020-01-09 21:23:16 +0100
committerPatrick Rudolph <siro@das-labor.org>2020-01-12 19:16:40 +0000
commitcbbfb702f693c1bbaf83a9d3d8a3c0caabda1814 (patch)
tree7c62c47ebcd6d02165993dd3a47d00b25bc4c146 /src/arch/x86/include
parent1862b503a46ae1e755b905dcc3570c8f7e3c2d29 (diff)
include/arch/romstage: Fix typo
Change-Id: Ie0c80792210ded7f81184b60ba2b0b51c13db283 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r--src/arch/x86/include/arch/romstage.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h
index 86d4e63eda..83d15e420b 100644
--- a/src/arch/x86/include/arch/romstage.h
+++ b/src/arch/x86/include/arch/romstage.h
@@ -75,7 +75,7 @@ void prepare_and_run_postcar(struct postcar_frame *pcf);
* tears down CAR and loads ramstage. The postcar_frame object
* indicates how to set up the frame. If caching is enabled at
* the time of the call it is up to the platform code to handle
- * coherency with dirty lines in the cache using some mechansim
+ * coherency with dirty lines in the cache using some mechanism
* such as platform_prog_run() because run_postcar_phase()
* utilizes prog_run() internally.
*/