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authorLee Leahy <leroy.p.leahy@intel.com>2015-06-12 17:30:33 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-06-17 11:56:01 +0200
commit2da9524aaf90b6b2f4d7fab81bfc82c9829e3d32 (patch)
tree54b59f36a0cefd98d8d3286e6bd5bbf7ab3c8609 /src/arch/x86/include
parent63a3e1ec7f49222c670d08424cbc7fc7f46ee7b0 (diff)
x86 cpu: Allow some cpuid functions during romstage
Allow calls to cpu_phys_address_size and its support functions during romstage. This enables the proper display of MTRRs during romstage without duplicating this code. BRANCH=none BUG=None TEST=Build and run on cyan Change-Id: I6f6465c150a683ce91f1494ebb5d9ac60b75b795 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6bfd517088b6a2e8a5958a837e6c8c471de19fd0 Original-Change-Id: I429f9beb69298836acdd71d17a7bcb717939dfc2 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/277392 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Commit-Queue: Leroy P Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10561 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/arch/x86/include')
-rw-r--r--src/arch/x86/include/arch/cpu.h6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index ebb7cdfdfb..851b58dd49 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -142,8 +142,12 @@ static inline unsigned int cpuid_edx(unsigned int op)
#define X86_VENDOR_ANY 0xfe
#define X86_VENDOR_UNKNOWN 0xff
-int cpu_phys_address_size(void);
+#define CPUID_FEATURE_PAE (1 << 6)
+#define CPUID_FEATURE_PSE36 (1 << 17)
+
+int cpu_cpuid_extended_level(void);
int cpu_have_cpuid(void);
+int cpu_phys_address_size(void);
#ifndef __SIMPLE_DEVICE__