diff options
author | Nico Huber <nico.h@gmx.de> | 2018-10-10 22:44:20 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:08 +0000 |
commit | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (patch) | |
tree | 0d4c9dfb483b0bdea6aa490bede17a6051337335 /src/arch/x86/cf9_reset.c | |
parent | 73c11194b0ea6a4fb93456fdff36cbd91838d4ec (diff) |
arch/x86: Implement common CF9 reset
It's very common across many x86 silicon vendors, so place it in
`arch/x86/`.
Change-Id: I06c27afa31e5eecfdb7093c02f703bdaabf0594c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86/cf9_reset.c')
-rw-r--r-- | src/arch/x86/cf9_reset.c | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/arch/x86/cf9_reset.c b/src/arch/x86/cf9_reset.c new file mode 100644 index 0000000000..c28e4488a6 --- /dev/null +++ b/src/arch/x86/cf9_reset.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/cache.h> +#include <cf9_reset.h> +#include <console/console.h> +#include <halt.h> +#include <reset.h> + +/* + * A system reset in terms of the CF9 register asserts the INIT# + * signal to reset the CPU along the PLTRST# signal to reset other + * board components. It is usually the hardest reset type that + * does not power cycle the board. Thus, it could be called a + * "warm reset". + */ +void do_system_reset(void) +{ + dcache_clean_all(); + outb(SYS_RST, RST_CNT); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +/* + * A full reset in terms of the CF9 register triggers a power cycle + * (i.e. S0 -> S5 -> S0 transition). Thus, it could be called a + * "cold reset". + * Note: Not all x86 implementations comply with this defitinion, + * some may require additional configuration to power cycle. + */ +void do_full_reset(void) +{ + dcache_clean_all(); + outb(FULL_RST | SYS_RST, RST_CNT); + outb(FULL_RST | RST_CPU | SYS_RST, RST_CNT); +} + +void system_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + do_system_reset(); + halt(); +} + +void full_reset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + cf9_reset_prepare(); + do_full_reset(); + halt(); +} |