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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-02-10 16:03:54 -0700 |
|---|---|---|
| committer | Marc Jones <marc@marcjonesconsulting.com> | 2017-03-07 23:01:36 +0100 |
| commit | 91dea4a6482cf6ebe4d4bc434fbcd566cedb3941 (patch) | |
| tree | d6e99903be2abc4b64b9fe7a45969fc51d7ebb63 /src/arch/x86/cbmem.c | |
| parent | 7b0b9f0d418712613ce1eba4ad392c2def958285 (diff) | |
amd/pi/hudson: Add early SPI setup
Add some generic functions that can configure the SPI interface to
have faster performance.
Given that the hudson files are used across many generations of FCHs,
make sure to refer to the appropriate BKDG or RRG before using the
functions. Notable differences:
* Hudson 1 defines read mode in CNTRL0 differently than later gens
* Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows
setting FastSpeed as well
* Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100
controller
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0)
Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18442
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/arch/x86/cbmem.c')
0 files changed, 0 insertions, 0 deletions