diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-06-16 10:34:04 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-23 17:22:44 +0200 |
| commit | 321a6a94f974257a96e753dc013be58d69938e05 (patch) | |
| tree | 4698dcd8fb121181a78839f42f6b9ce0421fa732 /src/arch/x86/cbmem.c | |
| parent | 3fd57d8239e036ef203e6d1c8db111b7395214db (diff) | |
rockchip/rk3399: fix sdram training issue
After write leveling for all ranks, check the
PHY_CLK_WRDQS_SLAVE_DELAY result, if the two ranks in one slice both
meet (0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20) or
(0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0), enable PHY_WRLVL_EARLY_FORCE_ZERO
for this slice, and trigger write leveling again.
BRANCH=none
BUG=chrome-os-partner:54144
TEST=run "stressapptest -M 1024 -s 1000" and pass
Change-Id: I1a0e4e888eb62b5fae5b5e5437a385e8660a246d
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 717cbac97b2045f2934e99859ce405aa3637b1c4
Original-Change-Id: Ic0d7c59404e870a7108ed64bbf3215fcc2d0973e
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/351825
Reviewed-on: https://review.coreboot.org/15300
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/arch/x86/cbmem.c')
0 files changed, 0 insertions, 0 deletions