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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-30 14:03:51 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-10-20 14:43:40 +0000 |
| commit | 9efb0c082512240f58001698b22d3c8472669156 (patch) | |
| tree | 36954f4dd83e75e396687d34deaa80f666931346 /src/arch/x86/car.ld | |
| parent | 1915ec1fe74a0f65d0e75464e176e5692bf27190 (diff) | |
arch/x86: Only use .bss from car.ld when running XIP
Some platform run early stages like romstage and verstage from CAR
instead of XIP. This allows to link them like other arch inside the
_program region. This make in place LZ4 decompression possible as it
needs a bit of extra place to extract the code which is now provided by
the .bss.
Tested on up/squared (Intel APL).
Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/arch/x86/car.ld')
| -rw-r--r-- | src/arch/x86/car.ld | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 132937f4ee..47afd78ba2 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -59,6 +59,7 @@ * cbmem console. This is useful for clearing this area on a per-stage * basis when more than one stage uses cache-as-ram. */ +#if ENV_SEPARATE_BSS . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; /* Allow global uninitialized variables for stages without CAR teardown. */ @@ -69,6 +70,7 @@ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; RECORD_SIZE(bss) +#endif #if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE) _shadow_size = (_ebss - _car_region_start) >> 3; |