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| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-02 16:19:29 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-13 13:55:50 +0000 |
| commit | b0d3a019413d179d624690ff4065c84cdd759584 (patch) | |
| tree | ecb7de5786c7c9a69e7e0721bff7c6e0abbb405f /src/arch/x86/c_start.S | |
| parent | 1ac0dc164d81f28602668cdb559b44f18dd4227d (diff) | |
soc/intel/alderlake: Define soc_get_pcie_rp_type
In order to distinguish PCH from CPU PCIe RPs, define the
soc_get_pcie_rp_type function for Alder Lake. While we're
here, add PCIe RP group definitions for PCH-M chipsets.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7438513e10b7cea8dac678b97a901b710247c188
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/arch/x86/c_start.S')
0 files changed, 0 insertions, 0 deletions