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authorStefan Reinauer <reinauer@chromium.org>2011-06-22 16:39:19 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2011-10-21 23:34:30 +0200
commitd1bc331855caab351a70676b5085787292a45fea (patch)
tree8d0ddcf777c4b7330e02495982f1f718f56d27fc /src/arch/x86/boot
parentb6010b8e70c25f93773bc464457f69fd4bb8a82e (diff)
Extend coreboot table entry for serial ports
Add information about memory mapped/io mapped base addresses. and fix up libpayload to use the same structures Signed-off-by: Stefan Reinauer <reinauer@google.com> Change-Id: I5f7b5eda6063261b9acb7a46310172d4a5471dfb Reviewed-on: http://review.coreboot.org/261 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/arch/x86/boot')
-rw-r--r--src/arch/x86/boot/coreboot_table.c15
1 files changed, 13 insertions, 2 deletions
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index cdfc0c1d8d..78ff97d21b 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -112,7 +112,19 @@ static struct lb_serial *lb_serial(struct lb_header *header)
serial = (struct lb_serial *)rec;
serial->tag = LB_TAG_SERIAL;
serial->size = sizeof(*serial);
- serial->ioport = CONFIG_TTYS0_BASE;
+ serial->type = LB_SERIAL_TYPE_IO_MAPPED;
+ serial->baseaddr = CONFIG_TTYS0_BASE;
+ serial->baud = CONFIG_TTYS0_BAUD;
+ return serial;
+#elif CONFIG_CONSOLE_SERIAL8250MEM
+ struct lb_record *rec;
+ struct lb_serial *serial;
+ rec = lb_new_record(header);
+ serial = (struct lb_serial *)rec;
+ serial->tag = LB_TAG_SERIAL;
+ serial->size = sizeof(*serial);
+ serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+ serial->baseaddr = uartmem_getbaseaddr();
serial->baud = CONFIG_TTYS0_BAUD;
return serial;
#else
@@ -131,7 +143,6 @@ static void add_console(struct lb_header *header, u16 consoletype)
console->size = sizeof(*console);
console->type = consoletype;
}
-
#endif
static void lb_console(struct lb_header *header)