diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-17 15:41:37 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-06-20 19:50:04 +0200 |
| commit | 2ca2afe760bf1f78ee410749332d85f9413a9f3a (patch) | |
| tree | 7040bede772c6b50ee00d6d04ff5205d70f77ccb /src/arch/x86/boot/tables.c | |
| parent | b3594ab4899aebf3883694fabe469a414dd9a799 (diff) | |
ACPI S3 support: Add acpi_s3_resume_allowed()
Add this to reduce the amount of preprocessor conditionals used in the source,
compiler currently resolves this to a constant.
Once we have gone through all #if CONFIG_HAVE_ACPI_RESUME cases, we may change
the implementation to enable/disable S3 support runtime.
Change-Id: I0e2d9f81e2ab87c2376a04fab38a7c951cac7a07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6060
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/x86/boot/tables.c')
| -rw-r--r-- | src/arch/x86/boot/tables.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 42e431e06e..16c752a154 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -192,19 +192,15 @@ void write_tables(void) post_code(0x9e); -#if CONFIG_HAVE_ACPI_RESUME -/* Only add CBMEM_ID_RESUME when the ramstage isn't relocatable. */ -#if !CONFIG_RELOCATABLE_RAMSTAGE /* Let's prepare the ACPI S3 Resume area now already, so we can rely on * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); -#endif -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB - cbmem_add(CBMEM_ID_RESUME_SCRATCH, CONFIG_HIGH_SCRATCH_MEMORY_SIZE); -#endif -#endif + if (HIGH_MEMORY_SAVE && acpi_s3_resume_allowed()) + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); + + if (HIGH_MEMORY_SCRATCH && acpi_s3_resume_allowed()) + cbmem_add(CBMEM_ID_RESUME_SCRATCH, HIGH_MEMORY_SCRATCH); #define MAX_COREBOOT_TABLE_SIZE (32 * 1024) post_code(0x9d); |