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authorSubrata Banik <subratabanik@google.com>2023-01-16 13:24:47 +0530
committerFelix Held <felix-coreboot@felixheld.de>2023-01-17 19:25:13 +0000
commit55812d6430b3bcab3961943621fe2784a3e2b79a (patch)
tree71961e4cdcebe0c412ee6add95a7045b030138dd /src/arch/x86/boot.c
parentb486fe95bf455008d5d5c6df7e1c1fc836e9ccd1 (diff)
soc/intel/alderlake: Avoid redundant chipset programming in romstage
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/x86/boot.c')
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