diff options
author | Duncan Laurie <dlaurie@chromium.org> | 2016-05-09 11:08:46 -0700 |
---|---|---|
committer | Duncan Laurie <dlaurie@google.com> | 2016-05-16 19:55:59 +0200 |
commit | abe2de8854fe1d1ed2b836da3069470dd6b04d6c (patch) | |
tree | 6e1f96795733229984972ef8329a3785f51a5727 /src/arch/x86/acpigen.c | |
parent | f7c3876c28634a70390edeb527c865516444e627 (diff) |
acpigen: Add functions to generate _STA() and _PRW()
Add helper functions for generating some common objects:
acpigen_write_STA(status) will generate a status method that will
indicate the device status as provided:
Method (_STA) { Return (status) }
Full status byte configuration is possible and macros are provided for
the common status bytes used for generated code:
ACPI_STATUS_DEVICE_ALL_OFF = 0x0
ACPI_STATUS_DEVICE_ALL_ON = 0xF
acpigen_write_PRW() will generate a Power Resoruce for Wake that describes
the GPE that will wake a particular device:
Name (_PRW, Package (2) { wake, level }
Change-Id: I10277f0f3820d272d3975abf34b9a8de577782e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/14795
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86/acpigen.c')
-rw-r--r-- | src/arch/x86/acpigen.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e051c822e6..74efbb0534 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -449,6 +449,17 @@ void acpigen_write_device(const char *name) acpigen_emit_namestring(name); } +void acpigen_write_STA(uint8_t status) +{ + /* + * Method (_STA, 0, NotSerialized) { Return (status) } + */ + acpigen_write_method("_STA", 0); + acpigen_emit_byte(0xa4); + acpigen_write_byte(status); + acpigen_pop_len(); +} + /* * Generates a func with max supported P-states. */ @@ -503,6 +514,18 @@ void acpigen_write_TPC(const char *gnvs_tpc_limit) acpigen_pop_len(); } +void acpigen_write_PRW(u32 wake, u32 level) +{ + /* + * Name (_PRW, Package () { wake, level } + */ + acpigen_write_name("_PRW"); + acpigen_write_package(2); + acpigen_write_integer(wake); + acpigen_write_integer(level); + acpigen_pop_len(); +} + void acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat, u32 control, u32 status) { |