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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-05 18:41:00 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-11 19:22:42 +0200 |
| commit | 2030d257d19920904ad370509404145c18627fac (patch) | |
| tree | 7c6b095d0439b7e42fce52d7759c08bf6692cda1 /src/arch/x86/Kconfig | |
| parent | db601b68182df47a28b106ba07e97f222ff39140 (diff) | |
arch/x86: Support "weak" BIST and timestamp save routines
Not all x86 architectures support the mm register set. The default
routine that saves BIST in mm0 and a "weak" routine that saves the TSC
value in mm2:mm1. Select the Kconfig value
BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP to provide a replacement routine to
save the BIST and timestamp values.
TEST=Build and run on Amenia and Galileo Gen2.
Change-Id: I8119e74664ac3522c011767d424d441cd62545ce
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15126
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/x86/Kconfig')
| -rw-r--r-- | src/arch/x86/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 1fea99ac3b..b6073c36ff 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -133,6 +133,15 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config BOOTBLOCK_RESETS string +config BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP + bool + default n + help + Select this value to provide a routine to save the BIST and timestamp + values. The default code places the BIST value in MM0 and the + timestamp value in MM2:MM1. Another file is necessary when the CPU + does not support the MMx register set. + config HAVE_CMOS_DEFAULT def_bool n |