diff options
| author | Lennart Eichhorn <lennarteichhorn@googlemail.com> | 2023-12-01 16:18:14 +0100 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2023-12-09 15:27:36 +0000 |
| commit | bf7eba7add1458ee8c5de58c4c4f16048ec11a08 (patch) | |
| tree | 579599fac315d15916643b99e17071acaec6c5da /src/arch/riscv | |
| parent | e06ebcd530cafd1cc89938bde80af45321d6bcaa (diff) | |
arch/riscv/payload: Remove old RISC-V CSR names
LLVM/clang 17 removed support for CSR names that are no longer included
in the RISC-V ISA Manual Privileged Specification since version 1.12.
Related LLVM commit: https://reviews.llvm.org/D149278
Change-Id: I7c8f2a06a109333f95230bf0a3056c8d5c8a9132
Signed-off-by: Lennart Eichhorn <lennarteichhorn@googlemail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/payload.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index 3097ad1bf8..ee2ee8e45c 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -39,13 +39,6 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode) status = INSERT_FIELD(status, MSTATUS_MPIE, 0); switch (payload_mode) { - case RISCV_PAYLOAD_MODE_U: - status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U); - /* Trap vector base address point to the payload */ - write_csr(utvec, doit); - /* disable U-Mode interrupt */ - write_csr(uie, 0); - break; case RISCV_PAYLOAD_MODE_S: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S); /* Trap vector base address point to the payload */ |