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| author | Jonathan Zhang <jonzhang@meta.com> | 2022-12-01 17:13:41 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:34:55 +0000 |
| commit | a3311b9f0f891c6f7740967273d58be4c7f86ded (patch) | |
| tree | b1b1528272a76c019fb9875ee68f748c7686fdaf /src/arch/riscv | |
| parent | 64bfc675a5c21716a6931ca015354a721a0898c0 (diff) | |
acpi/acpi.c: update ACPI table revisions
Update SRAT table revision to 3 according to ACPI spec.
Add CEDT table revision according to CXL spec.
Change-Id: Iecc3a9892b0f8093013b2a426749e2ec5c00803b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions