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| author | Furquan Shaikh <furquan@google.com> | 2016-04-19 15:49:23 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2016-04-21 08:24:33 +0200 |
| commit | 581c42807d358a66c2a4b3680d465a7069feb2f4 (patch) | |
| tree | 08c7bf01437273cb5532351bb3e2b839d0556f40 /src/arch/riscv | |
| parent | defbdcf3e58a7148ecd3c448e4d1e6683d54bd22 (diff) | |
soc/intel/apollolake: Set default memory type to uncacheable
Set the default memory type in MTRRCap register to 0. This ensures
that even if the MTRR Enable bit is set in MTRRCap register, the
default memory type is still uncacheable.
Change-Id: I63e7993f8b65dabbab60e7c1bb8d6d89ef4da9ee
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/14428
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions