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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-01-18 21:43:30 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-01-20 01:28:01 +0000 |
| commit | 4e818c5309d1efc79dad2771eaae0c37e6a07315 (patch) | |
| tree | c6d380efa136889da4a6c444779eb5d6759b786f /src/arch/riscv | |
| parent | ce60fb1d6305744ea7655c57b1c1efbf8451a6bc (diff) | |
soc/amd/*/chip: factor out FSP-S call
Move the call into the FSP code to a file in the common AMD FSP code to
isolate the FSP-specific parts of the code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions