diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-06-01 11:06:49 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-02 04:07:55 +0000 |
| commit | 550fa21776b757207df025cee8f1ffaf9c680793 (patch) | |
| tree | 4e956f8b66692ce25727a2c5b47ee104af1256a5 /src/arch/riscv | |
| parent | 64b29990dcf6af87f50ea77cd0cb3d742e5d5b75 (diff) | |
soc/intel/common: Add edge trigger configuartion for IOAPIC IRQ mode
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85daa
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/26730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions