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| author | Tim Chu <Tim.Chu@quantatw.com> | 2020-12-14 23:30:13 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-05 09:41:56 +0000 |
| commit | 3d6d1075b2ba17a357143f518715a911e09b38ec (patch) | |
| tree | 0d55c034468d65273f1c06c068ecb9cb4a59825b /src/arch/riscv | |
| parent | 40d45996d8efd3646d1b6dac7ae2d7d578eeb6f4 (diff) | |
soc/intel/xeon_sp/cpx: Override SMBIOS type 4 max speed
Override SMBIOS type 4 max speed. This field should be maximum speed
supported by the system. 3900MHz is expected for Cooper Lake.
Tested=Execute "dmidecode -t 4" to check max speed is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I67edf657a2fe66b38e08056d558e1b360c4b8adc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions