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| author | Julien Viard de Galbert <jviarddegalbert@online.net> | 2018-03-29 14:43:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-24 14:03:47 +0000 |
| commit | 2f66c709f481aec055809ac30afea094f036a136 (patch) | |
| tree | b1d6d63ddc84573d9288224a3854a0fb6cf12b85 /src/arch/riscv | |
| parent | ab1227226ebd78b40783cb200e60711b900352f0 (diff) | |
soc/intel/denverton_ns: Enable Fast Strings
Change-Id: I7cee3c40299abf14a24128b1ac14f1823f87a0e1
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25431
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions