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| author | Angel Pons <th3fanbus@gmail.com> | 2021-03-30 10:49:24 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-06 07:09:23 +0000 |
| commit | cc36c4c235eb8e36d5a48477fadc6fb08997c1f2 (patch) | |
| tree | 488f8e660760dc1a7d75ddf84f95e0b2a25d19b0 /src/arch/riscv | |
| parent | 52e61945588bc327844acc4658426861d63ad189 (diff) | |
sb/intel/*/smihandler.c: Correct BIOS_CNTL access width
The BIOS_CNTL register is 8 bits wide on all affected platforms.
Change-Id: Iaf9267cf27847d54ed50e1f9ae29011d0e99cf8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51939
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions