summaryrefslogtreecommitdiff
path: root/src/arch/riscv
diff options
context:
space:
mode:
authorAndrey Petrov <andrey.petrov@intel.com>2016-06-27 13:39:34 -0700
committerMartin Roth <martinroth@google.com>2016-08-28 18:38:48 +0200
commit3f4aece4e07b15a5a2d191873da04b88c8e87049 (patch)
tree95656eb37744843a4e9586c625451b55a5e17251 /src/arch/riscv
parent7f72c9b30ec543fc5d485dca5f15790d2c4b03f3 (diff)
soc/intel/apollolake: Add CQOS CAR implementation
Add new option to set up Cache-As-RAM by using CQOS, Cache Quality of Service. CQOS allows setting ways of cache in no-fill mode, while keeping other ways in regular evicting mode. This effectively allows using CAR and cache simultaneously. BUG=chrome-os-partner:51959 TEST=switch from NEM to CQOS and back, boot Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15455 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions