diff options
| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-02-18 16:06:21 -0800 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2016-02-19 05:42:32 +0100 |
| commit | f16d904192dc9173c526ae20eb26c910caf21fa2 (patch) | |
| tree | abb38abdd1f19bbfdb31a12dd398966e05d87e06 /src/arch/riscv | |
| parent | deba4e8560fdfc782168920321d7cb38b356ebe5 (diff) | |
RISC-V: Make inline asm usage safer
Change-Id: Id547c98e876e9fd64fa4d12239a2608bfd2495d2
Signed-off-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-on: https://review.coreboot.org/13735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/arch/riscv')
| -rw-r--r-- | src/arch/riscv/trap_handler.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 16b66d8314..53bcbf98c1 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -84,20 +84,18 @@ void handle_supervisor_call(trapframe *tf) { void trap_handler(trapframe *tf) { write_csr(mscratch, tf); - int cause = 0; - void* epc = 0; - void* badAddr = 0; + uintptr_t cause; + void *epc; + void *badAddr; // extract cause - asm("csrr t0, mcause"); - asm("move %0, t0" : "=r"(cause)); + asm("csrr %0, mcause" : "=r"(cause)); // extract faulting Instruction pc epc = (void*) tf->epc; // extract bad address - asm("csrr t0, mbadaddr"); - asm("move %0, t0" : "=r"(badAddr)); + asm("csrr %0, mbadaddr" : "=r"(badAddr)); switch(cause) { case 0: |