diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-09-21 17:05:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-10-07 17:33:38 +0200 |
| commit | f08f38883ea1a5c12bd1ece1736e336c20645e7c (patch) | |
| tree | c32dc6a6e53627ee449f9236c74c808272c9a731 /src/arch/riscv | |
| parent | c9fea5cdec8214703edcea9ea3012f37a37b1c3c (diff) | |
google/gru: set W2W_DIFFCS_DLY to 5
PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666.
For per cs training, the controller should consider the PHY
delay line switch time and there should be more cycles to
switch the delay line, so update the W2W_DIFFCS_DLY_ value
from 0x1 to 0x5.
BRANCH=none
BUG=chrome-os-partner:56940
TEST=do memtester on kevin board, and pass
Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc
Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/387506
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16721
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/arch/riscv')
0 files changed, 0 insertions, 0 deletions