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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:37:52 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-24 09:16:19 +0000
commitc94b38ec1336fa6b90a77b82582feb9093d8a274 (patch)
tree652e36c19f0c40f49686b01f12118d3186f741dc /src/arch/riscv
parent78546c513473994510957b180340c60240be1ac4 (diff)
src/arch: Drop unneeded empty lines
Change-Id: Ic86d2e6ad00cf190a2a728280f1a738486cb18c8 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44591 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/riscv')
-rw-r--r--src/arch/riscv/include/vm.h1
-rw-r--r--src/arch/riscv/misaligned.c2
-rw-r--r--src/arch/riscv/sbi.c1
3 files changed, 0 insertions, 4 deletions
diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h
index 5501a0c710..c1894c70ca 100644
--- a/src/arch/riscv/include/vm.h
+++ b/src/arch/riscv/include/vm.h
@@ -12,7 +12,6 @@
void mstatus_init(void); // need to setup mstatus so we know we have virtual memory
-
#define DEFINE_MPRV_READ_FLAGS(name, type, insn, flags) \
static inline type name(type *p); \
static inline type name(type *p) \
diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c
index 244081f384..a17b7dd454 100644
--- a/src/arch/riscv/misaligned.c
+++ b/src/arch/riscv/misaligned.c
@@ -131,7 +131,6 @@ static struct memory_instruction_info *match_instruction(uintptr_t insn)
return NULL;
}
-
static int fetch_16bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
{
uint16_t ins = mprv_read_mxr_u16((uint16_t *)vaddr);
@@ -157,7 +156,6 @@ static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size)
return -1;
}
-
void handle_misaligned(trapframe *tf)
{
uintptr_t insn = 0;
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index 38fc05e210..654bef03d6 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -49,7 +49,6 @@ static uintptr_t sbi_clear_ipi(void)
return 0;
}
-
/*
* sbi is triggered by the s-mode ecall
* parameter : register a0 a1 a2