diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2016-02-10 10:56:06 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-19 19:50:10 +0100 |
| commit | e0969aec2573872b9f528e33edd2cf3fb84c5948 (patch) | |
| tree | 25c7b837e62b40d6261ac9a58a190dc321e736a4 /src/arch/riscv/trap_util.S | |
| parent | f6ada1c30755f3de22942996bfcf6490a9b7b6e4 (diff) | |
x86: add coreboot table entry for TSC info
The 8254 (Programmable Interrupt Timer) is becoming optional
on x86 platforms -- either from saving power or not including it
at all. To allow a payload to still use a TSC without doing
calibration provide the TSC frequency information in the coreboot
tables. That data is provided by code/logic already employed
by platform. If tsc_freq_mhz() returns 0 or
CONFIG_TSC_CONSTANT_RATE is not selected the coreboot table
record isn't created.
BUG=chrome-os-partner:50214
BRANCH=glados
TEST=With all subsequent patches confirmed TSC is picked up in
libpayload.
Change-Id: Iaeadb85c2648587debcf55f4fa5351d0c287e971
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13670
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
0 files changed, 0 insertions, 0 deletions