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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-07-15 13:31:09 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-07-19 20:20:13 +0200 |
| commit | 64011880240cea5a3f8b1177853c7992a2d99ea8 (patch) | |
| tree | 6f06cd735d182511d022d551d4a31d78185930a0 /src/arch/riscv/trap_util.S | |
| parent | fcd51ffae86752f2794e1e5998b84f7119b7f091 (diff) | |
soc/intel/common: Add reset_prepare() for common reset
Some Intel SoC may need preparation before reset can be properly
handled. Add callback that chip/soc code can implement.
BUG=chrome-os-partner:55055
Change-Id: I45857838e1a306dbcb9ed262b55e7db88a8944e5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
0 files changed, 0 insertions, 0 deletions