diff options
| author | Maximilian Brune <maximilian.brune@9elements.com> | 2024-08-12 03:47:41 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-20 12:54:12 +0000 |
| commit | db1e9ce832c4b8aa5d1355b09e353789756ab86a (patch) | |
| tree | 7a540c12731078de43ae237199d22a548bf3888b /src/arch/riscv/trap_util.S | |
| parent | a985352350b5efa7388cdf9e4db8bc2fac25443f (diff) | |
arch/riscv: Remove ram probing
Previously RAM probing was necessary for our QEMU-RISCV target in order
to find the available amount of memory.
Now we get the memory from the devicetree propagated by QEMU, so there
is no reason to keep it anymore.
Tested:
Start QEMU-RISCV and cause an exception to make sure the trap handler
still works.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9b1e0dc78fc2a66d6085fe99a71245ff46f8e63c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83873
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/trap_util.S')
| -rw-r--r-- | src/arch/riscv/trap_util.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index d6a93b0ced..d81f884b00 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -120,8 +120,7 @@ trap_entry: mv a0,sp # put trapframe as first argument - LOAD t0, trap_handler - jalr t0 + jal trap_handler trap_return: restore_regs |