diff options
| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-21 19:37:03 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-28 18:53:04 +0200 |
| commit | fefc77afd0e739ec18129f8cd58781e15b9802e4 (patch) | |
| tree | ee1e71dc7d2973733196cdb730fc18e85dd70715 /src/arch/riscv/trap_handler.c | |
| parent | 719f9b53898bffa52395a1e25b616432eef6ff57 (diff) | |
arch/riscv: Show fault PC and load address on load access faults
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/trap_handler.c')
| -rw-r--r-- | src/arch/riscv/trap_handler.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ff3be56f78..5b4d0b1801 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -122,6 +122,8 @@ void trap_handler(trapframe *tf) { break; case 5: printk(BIOS_DEBUG, "Trap: Load access fault\n"); + printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc); + printk(BIOS_DEBUG, "Load Address: %p\n", badAddr); break; case 6: printk(BIOS_DEBUG, "Trap: Store address misaligned\n"); |