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| author | Tim Chu <Tim.Chu@quantatw.com> | 2022-12-13 12:09:44 +0000 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-25 16:33:36 +0000 |
| commit | 5c1964058f5a9e1f144cbb0a004181f1d046afe4 (patch) | |
| tree | 790100e4030948e776fd19e27d2ae79851b5c360 /src/arch/riscv/tables.c | |
| parent | ab8435335660d24f0c11a747ab3ba12cb7932c18 (diff) | |
soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP support
Add support for Intel SPR-SP to uncore_acpi.c.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/arch/riscv/tables.c')
0 files changed, 0 insertions, 0 deletions