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| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-03-13 07:48:55 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:48:44 +0000 |
| commit | 09a106907ea7e53e206ea1db3d1639d0941a39fe (patch) | |
| tree | 38dcadd1c0e88ab492f73357ecc0c79d4c5a092c /src/arch/riscv/tables.c | |
| parent | d991bf1fb43f977e46bd63a815dd0c8ec2cc3a8e (diff) | |
soc/intel/cannonlake/bootblock: Fix FSP CAR
Fix FSP CAR on platforms that have ROM_SIZE of 32MiB.
CodeRegionSize must be smaller than or equal to 16MiB
to not overlap with LAPIC or the CAR area at 0xfef00000.
Tested on Intel CFL, the new code allows to boot using FSP-T.
Change-Id: I4dfee230c3cc883fad0cb92977c8f5570e1a927c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/arch/riscv/tables.c')
0 files changed, 0 insertions, 0 deletions