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authorPhilipp Hug <philipp@hug.cx>2018-12-01 18:17:18 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-07 11:37:53 +0000
commit968a23d2e0afcf3ead23d3075aecc5c6e27211e4 (patch)
tree224538a6d842bd87f15ea167c5b75b9a555a8570 /src/arch/riscv/smp.c
parent6ee37ef59ddf5e7f005e0aa24541b190384ab87c (diff)
riscv: fix non-SMP support
Use CONFIG_CPU_MAX which defaults to 1 instead of CONFIG_RISCV_HART_NUM. The default value of CONFIG_RISCV_HART_NUM was 0 and cause a jump to address 0. Add a die() call to fail gracefully. Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/c/29993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xiang Wang <wxjstz@126.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch/riscv/smp.c')
-rw-r--r--src/arch/riscv/smp.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 8d07d39ded..8942ec5b93 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -55,7 +55,7 @@ void smp_pause(int working_hartid)
/* waiting for other Hart to enter the halt */
do {
barrier();
- } while (SYNCB + 1 < CONFIG_RISCV_HART_NUM);
+ } while (SYNCB + 1 < CONFIG_MAX_CPUS);
/* initialize for the next call */
SYNCA = 0;
@@ -72,14 +72,17 @@ void smp_resume(void (*fn)(void *), void *arg)
if (fn == NULL)
die("must pass a non-null function pointer\n");
- for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++) {
+ for (int i = 0; i < CONFIG_MAX_CPUS; i++) {
OTHER_HLS(i)->entry.fn = fn;
OTHER_HLS(i)->entry.arg = arg;
}
- for (int i = 0; i < CONFIG_RISCV_HART_NUM; i++)
+ for (int i = 0; i < CONFIG_MAX_CPUS; i++)
if (i != hartid)
set_msip(i, 1);
+ if (HLS()->entry.fn == NULL)
+ die("entry fn not set\n");
+
HLS()->entry.fn(HLS()->entry.arg);
}