diff options
| author | Philipp Hug <philipp@hug.cx> | 2019-02-06 06:48:51 +0100 |
|---|---|---|
| committer | ron minnich <rminnich@gmail.com> | 2019-02-13 04:49:14 +0000 |
| commit | b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 (patch) | |
| tree | f1a673efd5da4bcd24886b7c049335f52b8c1c75 /src/arch/riscv/smp.c | |
| parent | 540a66404591ef41e2581df01647e5788ef0c808 (diff) | |
riscv: Add initial support for 32bit boards
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/smp.c')
| -rw-r--r-- | src/arch/riscv/smp.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index 8942ec5b93..b32e4b8694 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -32,13 +32,13 @@ void smp_pause(int working_hartid) /* waiting for work hart */ do { barrier(); - } while (SYNCA != 0x01234567); + } while (atomic_read(&SYNCA) != 0x01234567); clear_csr(mstatus, MSTATUS_MIE); write_csr(mie, MIP_MSIP); /* count how many cores enter the halt */ - __sync_fetch_and_add(&SYNCB, 1); + atomic_add(&SYNCB, 1); do { barrier(); @@ -49,17 +49,17 @@ void smp_pause(int working_hartid) } else { /* Initialize the counter and * mark the work hart into smp_pause */ - SYNCB = 0; - SYNCA = 0x01234567; + atomic_set(&SYNCB, 0); + atomic_set(&SYNCA, 0x01234567); /* waiting for other Hart to enter the halt */ do { barrier(); - } while (SYNCB + 1 < CONFIG_MAX_CPUS); + } while (atomic_read(&SYNCB) + 1 < CONFIG_MAX_CPUS); /* initialize for the next call */ - SYNCA = 0; - SYNCB = 0; + atomic_set(&SYNCA, 0); + atomic_set(&SYNCB, 0); } #undef SYNCA #undef SYNCB |