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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2018-12-11 17:53:17 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-12-19 05:44:29 +0000
commitecf25fda862072c17701cd50bf233040ec210f4b (patch)
treef134fef0bbacd99f7b8d18d1d04908aeebe1516c /src/arch/riscv/sbi.c
parent7d81718cb863fd5d16e31c7fef203d5f63c87c97 (diff)
arch/riscv: Define and use SBI_ENOSYS
Change-Id: Ia7f409ebc7e50383a7e445ef8806953347501dab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/c/30175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx>
Diffstat (limited to 'src/arch/riscv/sbi.c')
-rw-r--r--src/arch/riscv/sbi.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index 832d4d3d97..e5408288af 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -113,7 +113,7 @@ void handle_sbi(trapframe *tf)
ret = send_ipi((uintptr_t *)arg0, IPI_SHUTDOWN);
break;
default:
- ret = -38;
+ ret = -SBI_ENOSYS;
break;
}
tf->gpr[10] = ret;