diff options
| author | Xiang Wang <wxjstz@126.com> | 2019-06-21 13:04:10 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-03-09 23:34:25 +0000 |
| commit | 52b81845de44dfa1af50e203c2cab9a953a628f1 (patch) | |
| tree | d7345f8fcb0d1f857affd2d5dc310ed2715bdd29 /src/arch/riscv/payload.c | |
| parent | 5787a4c53b56325dad364f11774b481fc27a9684 (diff) | |
arch/riscv: Add SMP support for exception handler
Change-Id: Ia1f97b82e329f6358061072f98278cf56b503618
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68841
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/payload.c')
| -rw-r--r-- | src/arch/riscv/payload.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c index ee2ee8e45c..443975bf40 100644 --- a/src/arch/riscv/payload.c +++ b/src/arch/riscv/payload.c @@ -6,6 +6,7 @@ #include <arch/encoding.h> #include <arch/smp/atomic.h> #include <console/console.h> +#include <mcall.h> #include <vm.h> /* Run OpenSBI and let OpenSBI hand over control to the payload */ @@ -47,6 +48,8 @@ void run_payload(struct prog *prog, void *fdt, int payload_mode) write_csr(sie, 0); /* disable MMU */ write_csr(satp, 0); + /* save stack to mscratch so trap_entry can use that as exception stack */ + write_csr(mscratch, MACHINE_STACK_TOP()); break; case RISCV_PAYLOAD_MODE_M: status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M); |