riscv: add support for OpenSBI

Call OpenSBI in M-Mode and use it to set up SBI and to lockdown the
platform. It will also jump to the specified payload when done.
This behaviour is similar to BL31 on aarch31.

The payload is 41KiB in size on qemu.

Tested on qemu-riscv:
Required to boot a kernel as OpenSBI's instruction emulation feature
is required on that virtual machine.

Tested on SiFive/unleashed:
The earlycon is working. No console after regular serial driver
should take over, which might be related to kernel config.

Change-Id: I2a178595bd2aa2e1f114cbc69e8eadd46955b54d
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

1 files changed, 41 insertions, 0 deletions

diff --git a/src/arch/riscv/opensbi.c b/src/arch/riscv/opensbi.c
new file mode 100644
index 0000000000..695c24f756
--- /dev/null
+++ b/src/arch/riscv/opensbi.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 9elements Agency GmbH <patrick.rudolph@9elements.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <sbi/fw_dynamic.h>
+#include <arch/boot.h>
+/* DO NOT INLCUDE COREBOOT HEADERS HERE */
+
+void run_opensbi(const int hart_id,
+		 const void *fdt,
+		 const void *opensbi,
+		 const void *payload,
+		 const int payload_mode)
+{
+	struct fw_dynamic_info info = {
+		.magic = FW_DYNAMIC_INFO_MAGIC_VALUE,
+		.version = FW_DYNAMIC_INFO_VERSION_MAX,
+		.next_mode = payload_mode,
+		.next_addr = (uintptr_t)payload,
+	};
+
+	csr_write(mepc, opensbi);
+	asm volatile (
+			"mv	a0, %0\n\t"
+			"mv	a1, %1\n\t"
+			"mv	a2, %2\n\t"
+			"mret" :
+			: "r"(hart_id), "r"(fdt), "r"(&info)
+			: "a0", "a1", "a2");
+}