arch/riscv: provide a monotonic timer

The RISC-V Privileged Architecture specification defines the Machine
Time Registers (mtime and mtimecmp) in section 3.1.15.

Makes it possible to use the generic udelay.
The timer is enabled using RISCV_USE_ARCH_TIMER for the lowrisc,
sifive and ucb soc.

Change-Id: I5139601226e6f89da69e302a10f2fb56b4b24f38
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/27434
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 4 deletions

diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c
index 65b8ecf02f..1909dbc5f1 100644
--- a/src/arch/riscv/misc.c
+++ b/src/arch/riscv/misc.c
@@ -16,7 +16,3 @@
 void init_timer(void)
 {
 }
-
-void udelay(unsigned int n)
-{
-}