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authorJonathan Neuschäfer <j.neuschaefer@gmx.net>2016-08-09 02:07:12 +0200
committerRonald G. Minnich <rminnich@gmail.com>2016-08-11 21:12:54 +0200
commit1394bba6bb9e8dc48afb4fe6107d8e64ee5e6855 (patch)
treecce5ebb12c6cc6760b90ec993f50a2be0d797d4f /src/arch/riscv/misc.c
parentc42b5917af50a1a0b6a64330e9cdd953c46102b7 (diff)
arch/riscv: Fix the page table setup code
In particular: - Fix the condition of the loop that fills the mid-level page table - Adhere to the format of sptbr Change-Id: I575093445edfdf5a8f54b0f8622ff0e89f77ccec Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16120 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/arch/riscv/misc.c')
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