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| author | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-19 16:20:27 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2020-11-24 12:02:06 +0000 |
| commit | f4721246db125e08b5e60a8a38a08cb92c478bd3 (patch) | |
| tree | 3c01103f94434430eb4cea4579dd419abbcb3e48 /src/arch/riscv/misaligned.c | |
| parent | f4f332dba992212165b4d8b755a220d27c267c01 (diff) | |
soc/intel/xeon_sp: Select INTEL_COMMON_BLOCK_TCO
TCO is configured by FSP. This mostly makes it possible to report TCO
events in SMM if enabled.
Change-Id: I4f81c7888e45ed01ee68b1d6e6a9986a4d735467
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47764
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/arch/riscv/misaligned.c')
0 files changed, 0 insertions, 0 deletions