diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-08-19 15:35:17 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-24 09:15:27 +0000 |
| commit | 78546c513473994510957b180340c60240be1ac4 (patch) | |
| tree | dc0c935f6e051d9647b86122f2f5f89926e55a1b /src/arch/riscv/misaligned.c | |
| parent | d3a74bb4fe305e5b2e6c74a6f777f549fad34b3b (diff) | |
edk2-stable202005/IntelFsp2Pkg: Add FSP*_ARCH_UPD.
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
ref:
- https://bugzilla.tianocore.org/show_bug.cgi?id=2781
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'src/arch/riscv/misaligned.c')
0 files changed, 0 insertions, 0 deletions