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| author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | 2022-05-25 14:47:13 +0800 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-28 03:39:55 +0000 |
| commit | 32e72ca0b74f3ebd8124d4a62a3f6777b6aba428 (patch) | |
| tree | da922c24400ec32b9ff44174c5ea37963f43a79b /src/arch/riscv/mcall.c | |
| parent | 455accd3f7cc761677cc4a2ffb417b5546597732 (diff) | |
mb/google/brask/variants/moli: correct empty tcss port
Correct empty tcss port to meet Moli's schematic design.
BUG=b:233834605
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id16744655010e246c8ca8d1050f71a6c6c63d2a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/arch/riscv/mcall.c')
0 files changed, 0 insertions, 0 deletions