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authorXiang Wang <wxjstz@126.com>2018-08-09 16:20:35 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-09-10 15:03:58 +0000
commitcda59b56ba1af83a64579901a5395c1b3c1bf519 (patch)
tree1ea1d63305663f76623b8db878e33f72b4867f82 /src/arch/riscv/include
parentaa5f821ee3313b869784eec25fab5da265225738 (diff)
riscv: update misaligned memory access exception handling
Support for more situations: floating point, compressed instructions, etc. Add support for redirect exception to S-Mode. Change-Id: I9983d56245eab1d458a84cb1432aeb805df7a49f Signed-off-by: Xiang Wang <wxjstz@126.com> Reviewed-on: https://review.coreboot.org/27972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Diffstat (limited to 'src/arch/riscv/include')
-rw-r--r--src/arch/riscv/include/arch/exception.h11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/arch/riscv/include/arch/exception.h b/src/arch/riscv/include/arch/exception.h
index fc57b3b55c..6fbbdf0a89 100644
--- a/src/arch/riscv/include/arch/exception.h
+++ b/src/arch/riscv/include/arch/exception.h
@@ -32,8 +32,7 @@
#include <stdint.h>
-typedef struct
-{
+typedef struct {
uintptr_t gpr[32];
uintptr_t status;
uintptr_t epc;
@@ -53,9 +52,9 @@ static inline void exception_init(void)
{
}
-void trap_handler(trapframe* tf);
-void handle_supervisor_call(trapframe* tf);
-void handle_misaligned_load(trapframe *tf);
-void handle_misaligned_store(trapframe *tf);
+void redirect_trap(void);
+void trap_handler(trapframe *tf);
+void handle_supervisor_call(trapframe *tf);
+void handle_misaligned(trapframe *tf);
#endif